View CS7054_260035.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Back
CS7054 Low Side PWM FET Controller
The CS7054 is a monolithic integrated circuit designed primarily to control the rotor speed of permanent magnet, direct current (DC) brush motors. It drives the gate of an N channel power MOSFET or IGBT with a user-adjustable, fixed frequency, variable duty cycle, pulse width modulated (PWM) signal. The CS7054 can also be used to control other loads such as incandescent bulbs and solenoids. Inductive current from the motor or solenoid is recirculated through an external diode. The CS7054 accepts a DC level input signal of 0 to 5.0 V to control the pulse width of the output signal. This signal can be generated by a potentiometer referenced to the on-chip 5.0 V linear regulator, or a filtered 0% to 100% PWM signal also referenced to the 5.0 V regulator. The IC is placed in a sleep state by pulling the CTL lead below 0.5 V. In this mode everything on the chip is shut down except for the on-chip regulator and the overall current draw is less than 275 A. There are a number of on-chip diagnostics that look for potential failure modes and can disable the external power MOSFET.
http://onsemi.com
DIP-14 N SUFFIX CASE 646 1 SO-16L DW SUFFIX CASE 751G 1
14
16
PIN CONNECTIONS AND MARKING DIAGRAMS
1 OUTPUT GND FLT COSC ROSC CTL NC DIP-14 1 OUTPUT GND FLT COSC ROSC CTL NC NC AWLYYWW 16 VCC NC PGND INH IADJ ISENSE+ ISENSE- VREG 14 VCC PGND INH IADJ ISENSE+ ISENSE- VREG
* * * * * * * *
Features 200 mA Peak PWM Gate Drive Output Patented Voltage Compensation Circuit 100% Duty Cycle Capability 5.0 V, 3.0% Linear Regulator Low Current Sleep Mode Overvoltage Protection Overcurrent Protection of External MOSFET/IGBT Output Inhibit
SO-16L A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week
ORDERING INFORMATION
Device CS7054YN14 CS7054YDW16 CS7054YDWR16 Package DIP-14 SO-16L Shipping 25 Units/Rail 46 Units/Rail
CS7054 AWLYYWW CS7054
SO-16L 1000 Tape & Reel
(c) Semiconductor Components Industries, LLC, 2001
1
January, 2001 - Rev. 12
Publication Order Number: CS7054/D
CS7054
MOT+
VBAT
42.5 H
RS 51 1000 F 1000 F OUTPUT GND FLT CS7054 COSC ROSC CTL NC IADJ ISENSE+ ISENSE- VREG VCC PGND INH 10 F
RGATE 6 0.01 F 1.0 M
MOT-
CFLT COSC
0.25 F 390 pF
RCS1 CCS 51 0.022 F RCS2 51 RSENSE 4.0 m
ROSC 105 k
PWM Input 10 k
10 k P1 100 k 10 k 10 F
10 k
10 k
10 k N1 10 k
Figure 1. Application Diagram
ABSOLUTE MAXIMUM RATINGS*
Rating Storage Temperature VCC Supply Voltage Range (Load Dump = 26 V w/Series 51 Resistor) VCC Peak Transient Voltage Input Voltage Range (at any input) Maximum Junction Temperature ESD Susceptibility (Human Body Model) Lead Temperature Soldering 1. 10 seconds max. 2. 60 seconds max above 183C *The maximum package power dissipation must be observed. Wave Solder (through hole styles only) Note 1. Reflow (SMD styles only) Note 2. Value -65 to 150 -0.3 to 30 40 -0.3 to 10 150 2.0 260 peak 230 peak Unit C V V V C kV C C
http://onsemi.com
2
CS7054
ELECTRICAL CHARACTERISTICS (8.0 V < VCC < 16 V; -40C < TA < 125C; unless otherwise specified.)
Characteristic VCC Supply Operating Current Supply Quiescent Current Overvoltage Shutdown Overvoltage Hysteresis Control (CTL) Control Input Current Sleep Mode Threshold Sleep Mode Hysteresis Current Sense Differential Voltage Sense IADJ Input Current Linear Regulator Output Voltage Inhibit Inhibit Threshold Inhibit Hysteresis External Drive (OUTPUT) Output Frequency Voltage to Duty Cycle Conversion Output Rise Time Output Fall Time Output Sink Current Output Source Current Output High Voltage Output Low Voltage ROSC = 105 k, COSC = 390 pF VCC = 13 V, CTL = 30% VREG VCC = 13 V, CTL = 70% VREG VCC = 13 V, RGATE = 6.0 , CGATE = 5.0 nF VCC = 13 V, RGATE = 6.0 , CGATE = 5.0 nF VCC = 13 V, RGATE = 6.0 , CGATE = 5.0 nF VCC = 13 V, RGATE = 6.0 , CGATE = 5.0 nF IOUT = 1.0 mA IOUT = -1.0 mA 17 26.3 69.5 - - - - VCC - 1.7 - 20 - - 0.25 0.3 400 400 - - 23 38.5 81.5 1.0 1.0 - - - 1.3 kHz % % s s mA mA V V - - 40 150 50 325 60 575 % VREG mV VCC = 13.2 V 4.85 5.00 5.15 V IADJ = 51.2% VREG and RCS1 = 51 IADJ = 0 V to 5.0 V 60.5 -5.0 - 0.3 79.5 2.0 mV A CTL = 0 V to 5.0 V - - -2.0 8.0 50 0.1 10 100 2.0 12 150 A % VREG mV VCC = 12 V - - - - - 18 150 5.0 170 19.5 325 10 275 21 500 mA A V mV Test Conditions Min Typ Max Unit
http://onsemi.com
3
CS7054
PACKAGE PIN DESCRIPTION
PACKAGE PIN # DIP-14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SO-16L 1 2 3 4 5 6 7, 8, 15 9 10 11 12 13 14 16 PIN SYMBOL OUTPUT GND FLT COSC ROSC CTL NC VREG ISENSE- ISENSE+ IADJ INH PGND VCC FUNCTION MOSFET Gate Drive. Ground. Fault time out capacitor. Oscillator capacitor. Oscillator resistor. Pulse width control input. No connection. 5.0 V linear regulator. Current sense minus. Current sense plus. Current limit adjust. Output Inhibit. Power ground for on chip clamp. Positive power supply input.
GND VCC
VREG
5.0 V Regulator
Overvoltage Clamp VCC PGND + _ CTL + _ Reset Triangle Oscillator S R Current Sense ISENSE+ Q + _ OUTPUT
+ _
INH
ISENSE- Timer Out In + _
IADJ
FLT COSC ROSC
Figure 2. Block Diagram http://onsemi.com
4
CS7054
TYPICAL PERFORMANCE CHARACTERISTICS
5.04
5.04 2.0 mA 100 A
5.02
2.0 mA
100 A
5.02
5.00 VREG VREG
5.00 5.0 mA 4.98 5.0 mA
4.98
4.96
4.96
4.94 -50
0
50 Temperature
100
150
4.94 -50
0
50 Temperature
100
150
Figure 3. VREG vs. Temperature @ VCC = 8.0 V
Figure 4. VREG vs. Temperature @ VCC = 12 V
5.04 2.0 mA 5.02 100 A
1.7 1.6 1.5 OUTPUT
5.00 VREG 5.0 mA 4.98
1.4 1.3 1.2
I = 2.0 mA
4.96 1.1 4.94 -50 0 50 Temperature 100 150 1.0 -50 0 50 Temperature 100 150
Figure 5. VREG vs. Temperature @ VCC = 16 V
Figure 6. OUTPUT Saturation Voltage (Sourcing Current) vs Temperature
1.3
I = 2.0 mA OUTPUT 1.2
1.1 -50
0
50 Temperature
100
150
Figure 7. OUTPUT Voltage (Sinking Current) vs Temperature http://onsemi.com
5
CS7054
APPLICATIONS INFORMATION
THEORY OF OPERATION Oscillator
The IC sets up a constant frequency triangle wave at the COSC lead whose frequency is determined by the external components ROSC and COSC by the following equation:
Frequency + 0.83 ROSC COSC
is compared to the oscillator voltage to produce the compensated duty cycle. The transfer is set up so that at VCC = 14 V the duty will equal VCTL divided by VREG. For example at VCC = 14 V, VREG = 5.0 V and VCTL = 2.5 V, the duty cycle would be 50% at the output. This would place a 7.0 V average voltage across the load. If VCC then drops to 10 V, the IC would change the duty cycle to 70% and hence keep the average load voltage at 7.0 V.
120 100 Duty Cycle (%) 80 60 40 20 0 10 VCC = 8.0 V VCC = 14 V VCC = 16 V
The peak and valley of the triangle wave are proportional to VCC by the following:
VVALLEY + 0.2 VPEAK + 0.8 VCC VCC
This is required to make the voltage compensation function properly. In order to keep the frequency of the oscillator constant the current that charges COSC must also vary with supply. ROSC sets up the current which charges COSC. The voltage across ROSC is 50% of VCC and therefore:
IROSC + 0.5 VCC ROSC
20
30
50 40 60 70 80 CTL Voltage (% of VREG)
90
100
IROSC is multiplied by two (2) internally and transferred to the COSC lead. Therefore:
V ICOSC +" CC ROSC
Figure 8. Voltage Compensation 5.0 V Linear Regulator
The period of the oscillator is:
T + 2COSC VPEAK * VVALLEY ICOSC
There is a 5.0 V, 5.0 mA linear regulator available at the VREG lead for external use. This voltage acts as a reference for many internal and external functions. It has a drop out of approximately 1.5 V at room temperature and does not require an external capacitor for stability.
Current Sense and Timer
The ROSC and COSC components can be varied to create frequencies over the range of 15 Hz to 25 kHz. With the suggested values of 105 k and 390 pF for ROSC and COSC respectively, the nominal frequency will be approximately 20 kHz. IROSC, at VCC = 14 V, will be 66.7 A. IROSC should not change over a more than 2:1 ratio and therefore COSC should be changed to adjust the oscillator frequency.
Voltage Duty Cycle Conversion
The IC differentially monitors the load current on a cycle by cycle basis at the ISENSE+ and ISENSE- leads. The differential voltage across these two leads is amplified internally and compared to the voltage at the IADJ lead. The gain, AV, is set internally and externally by the following equation:
AV + VI(ADJ) ISENSE) * ISENSE* + 37000 1000 ) RCS
The IC translates an input voltage at the CTL lead into a duty cycle at the OUTPUT lead. The transfer function incorporates ON Semiconductor's patented Voltage Compensation method to keep the average voltage and current across the load constant regardless of fluctuations in the supply voltage. The duty cycle is varied based upon the input voltage and supply voltage by the following equation:
Duty Cycle + 100% 2.8 VCTL VCC
The current limit (ILIM) is set by the external current sense resistor (RSENSE) placed across the ISENSE+ and ISENSE- terminals and the voltage at the IADJ lead.
ILIM + 1000 ) RCS 37000 VI(ADJ) RSENSE
An internal DC voltage equal to:
VDC + (1.683 VCTL) ) VVALLEY
The RCS resistors and CCS components form a differential low pass filter which filters out high frequency noise generated by the switching of the external MOSFET and the associated lead noise. RCS also forms an error term in the gain of the ILIM equation because the ISENSE+ and ISENSE-
http://onsemi.com
6
CS7054
leads are low impedance inputs thereby creating a good current sensing amplifier. Both leads source 50 A while the chip is in run mode. RCS should be much less than 1000 to minimize error in the ILIM equation. IADJ should be biased between 1.0 V and 4.0 V. When the current through the external MOSFET exceeds ILIM, an internal latch is set and the output pulls the gate of the MOSFET low for the remainder of the oscillator cycle (fault mode). At the start of the next cycle, the latch is reset and the IC reverts back to run mode until another fault occurs. If a number of faults occur in a given period of time, the IC "times out" and disables the MOSFET for a long period of time to let it cool off. This is accomplished by charging the CFLT capacitor each time an over current condition occurs. If a cycle goes by with no overcurrent fault occurring, an even smaller amount of charge will be removed from CFLT. If enough faults occur together, eventually CFLT will charge up to 2.4 V and the fault latch will be set. The fault latch will not be reset until the CFLT discharges to 0.6 V. This action will continue indefinitely if the fault persists. The off time and on time are set by the following:
Off Time + CFLT On Time + CFLT 2.4 V * 0.6 V 4.5 mA 2.4 V * 0.6 V IAVG Overvoltage Shutdown
The IC will disable the output during an overvoltage event. This is a real time fault event and does not set the internal latch and therefore is independent of the oscillator timing (i.e. asynchronous). There is no undervoltage lockout. The device will shutdown gracefully once it runs out of headroom. This happens at the point when VREG falls out of regulation.
Reverse Battery
The CS7054 will not survive a reverse battery condition. Therefore, a series diode is required between the battery and the VCC lead.
Load Dump
VCC is internally clamped to 30 V. It is recommended that a 51 resistor, (RS) is placed in series with VCC to limit the current flow into the IC in the event of a 40 V peak transient condition.
Using the CS7054 as a Frequency Converter
where:
IAVG + (295.5 mA DC) * [4.5 mA (1 * DC)]
IAVG + (300 mA
DC) * 4.5 mA
DC + PWM Duty Cycle Sleep State
Figure 9 shows the CS7054 configured for use as a frequency converter. In the setup shown, a 150 Hz square wave from a microprocessor is converted to a 10 kHz square wave. The duty cycle of each waveform is identical. The amplitude of the input waveform is 5.0 V, but does not need to be. The input amplitude requirement just needs to be high enough to switch the external bipolar transistor. The 10 kHz oscillator frequency is setup per the oscillator section of this data sheet. The external resistor divider composed of the 3.6 k and 6.2 k resistors supplies 5.0 V to the CTL pin when the input duty cycle is at 100%. This also makes the output waveform 100%. The RC filter (1.0 M and 0.1 F) sets up a pole at 1.6 Hz:
f+ 1+ 2pRC 1 2p 1 MW )
(6.2 k)(3.6 k) 6.2 k)3.6 k
This device will enter into a low current mode (< 275 A) when CTL lead is brought to less than 0.5 V. All functions are disabled in this mode, except for the regulator.
(0.1 mF)
+ 1.6 Hz
Inhibit
When the inhibit voltage is greater than 2.5 V the internal latch is set and the external MOSFET will be turned off for the remainder of the oscillator cycle. The latch is then reset at the start of the next cycle.
In this case, the pole is 2 orders of magnitude below the input waveform. Care must be taken to provide the appropriate DC level on the control pin in addition to providing the required response time. *Note the current limit feature of the CS7054 has been defeated by grounding the ISENSE+ and the ISENSE- pins and connecting the IADJ lead to VREG.
http://onsemi.com
7
CS7054
10 10 F VCC 0 f = 10 kHz
VBAT
OUTPUT GND FLT
VCC PGND INH
820 pF COSC 100 k 150 Hz 5.0 V 0 MCU 100 k 100 k Q2 Q1 100 k 3.6 k 6.2 k 1.0 M ROSC CTL NC
CS7054 IADJ ISENSE+ ISENSE- VREG
0.1 F
Figure 9. Frequency Converter
http://onsemi.com
8
CS7054
PACKAGE DIMENSIONS
DIP-14 N SUFFIX CASE 646-04 ISSUE M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.715 0.740 0.240 0.260 0.160 0.180 0.015 0.020 0.040 0.060 0.100 BSC 0.052 0.072 0.008 0.012 0.115 0.135 0.290 0.310 --10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 4.06 4.57 0.38 0.51 1.02 1.52 2.54 BSC 1.32 1.83 0.20 0.30 2.92 3.43 7.37 7.87 --10 _ 0.51 1.02
14
8
B
1 7
A F N -T-
SEATING PLANE
L C
K H G D 14 PL 0.13 (0.005)
M
J M
DIM A B C D F G H J K L M N
SO-16L DW SUFFIX CASE 751G-03 ISSUE B
D
16 M 9
A
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 10.15 10.45 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
B
1 16X
8
B TA
S
B B
S
0.25
M
A
h X 45 _
SEATING PLANE
M
8X
0.25
E
A1
14X
e
T
C
PACKAGE THERMAL DATA Parameter RJC RJA Typical Typical DIP-14 48 85 SO-16L 23 105 Unit C/W C/W
http://onsemi.com
9
L
CS7054
Notes
http://onsemi.com
10
CS7054
Notes
http://onsemi.com
11
CS7054
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com Fax Response Line: 303-675-2167 or 800-344-3810 Toll Free USA/Canada N. American Technical Support: 800-282-9855 Toll Free USA/Canada EUROPE: LDC for ON Semiconductor - European Support German Phone: (+1) 303-308-7140 (Mon-Fri 2:30pm to 7:00pm CET) Email: ONlit-german@hibbertco.com French Phone: (+1) 303-308-7141 (Mon-Fri 2:00pm to 7:00pm CET) Email: ONlit-french@hibbertco.com English Phone: (+1) 303-308-7142 (Mon-Fri 12:00pm to 5:00pm GMT) Email: ONlit@hibbertco.com EUROPEAN TOLL-FREE ACCESS*: 00-800-4422-3781 *Available from Germany, France, Italy, UK, Ireland CENTRAL/SOUTH AMERICA: Spanish Phone: 303-308-7143 (Mon-Fri 8:00am to 5:00pm MST) Email: ONlit-spanish@hibbertco.com ASIA/PACIFIC: LDC for ON Semiconductor - Asia Support Phone: 303-675-2121 (Tue-Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong & Singapore: 001-800-4422-3781 Email: ONlit-asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-0031 Phone: 81-3-5740-2745 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local Sales Representative.
http://onsemi.com
12
CS7054/D

▲Up To Search▲

Price & Availability of CS7054

	To Download CS7054 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .